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AS1116
Datasheet - D e t a i l e d D e s c r i p t i o n
Feature Register (0x0E)
The Feature Register is used for enabling various features including switching the device into external clock mode, applying an external reset,
selecting code-B or HEX decoding, enabling or disabling blinking, enabling or disabling the SPI-compatible interface, setting the blinking rate,
and resetting the blink timing.
Note: At power-up the Feature Register is initialized to 0.
Table 19. Feature Register Summary
D7
blink_start
D6
sync
D5
blink_freq_sel
D4
blink_en
D3
NU
D2
decode_sel
D1
reg_res
D0
clk_en
Table 20. Feature Register Bit Descriptions (Address (HEX) = 0xXE)
Addr: 0xXE
Feature Register
Enables and disables various device features.
Bit
Bit Name
Default
Access
Bit Description
External clock active.
D0
clk_en
0 R/W
0 = Internal oscillator is used for system clock.
1 = Pin CLK of the serial interface operates as system clock input.
Resets all control registers except the Feature Register.
0 = Reset Disabled. Normal operation.
D1
reg_res
0 R/W
1 = All control registers are reset to default state (except the Feature Register)
identically after power-up.
Note: The Digit Registers maintain their data.
Selects display decoding for the selected digits ( Table 9 on page 12 ).
D2
decode_sel
0 R/W
0 = Enable Code-B decoding (see Table 10 on page 12 ).
1 = Enable HEX decoding (see Table 11 on page 13 ).
D3
NU
Not used
D4
blink_en
0 R/W
Enables blinking.
0 = Disable blinking. 1 = Enable blinking.
Sets blink with low frequency (with the internal oscillator enabled):
D5
blink_freq_sel
0 R/W
0 = Blink period typically is 1 second (0.5s on, 0.5s off).
1 = Blink period is 2 seconds (1s on, 1s off).
Synchronizes blinking on the rising edge of pin LD. The multiplex and blink timing
D6
sync
0 R/W
counter is cleared on the rising edge of pin LD. By setting this bit in multiple devices, the
blink timing can be synchronized across all the devices.
Start Blinking with display enabled phase. When bit D4 (blink_en) is set, bit D7
D7
blink_start
0 R/W
determines how blinking starts.
0 = Blinking starts with the display turned off.
1 = Blinking starts with the display turned on.
No-Op Register (0xX0)
The No-Op Register is used when multiple AS1116 devices are cascaded in order to support displays with more than 8 digits. The cascading
must be done in such a way that all SDO pins are connected to SDI of the next AS1116 ( see Figure 21 on page 18 ). The LD and SCL sig-
nals are connected to all devices.
For example, if five devices are cascaded, in order to perform a write operation to the fifth device, the write-command must be followed by four
no-operation commands. When the LD signal goes high, all shift registers are latched. The first four devices will receive no-operation commands
and only the fifth device will receive the intended operation command, and subsequently update its register.
www.austriamicrosystems.com/LED-Driver-ICs/AS1116
Revision 1.08
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